1. Technical Field
Embodiments of the present invention relate to features of a Field Programmable Gate Array (FPGA) to enable the FPGA to be used as a memory controller. More particularly, the present invention relates to a memory controller that can be used in a stacked-die configuration to control one or more DRAM memory devices.
2. Related Art
Conventional processor-based systems use some form of memory controller in order to access memory devices and provide arbitration for devices connected to the memory controller ports such as processors or other peripherals. To address the need to configure a memory controller to provide maximum bandwidth when used with various processor systems, a programmable logic device such as a Field Programmable Gate Array (FPGA) has been used to create the memory controller. FPGAs can be used to provide a wide variety of these memory controllers, including single port and multiport memory controllers.
FIG. 1 is a block diagram showing components of a typical FPGA 102 that can be connected to a memory 150 for purposes of illustration. The memory 150 can be a Dynamic Random Access Memory (DRAM) device. The memory 150 can further be an FPGA using die stacking as illustrated in FIG. 2. For die stacking an FPGA, die 102 is stacked with the DRAM die 150 and can be interconnected with methods such as vias, or simply wire bonding. The stacked dies 102 and 150 can then be included in a single chip package to form a single system-level integrated circuit (referred to as a “system-in-a-package” or (SiP). The concept of die-stacking an FPGA with another DRAM is described in U.S. Pat. No. 7,068,072, entitled “Integrated Circuit with Interface Tile for Coupling to a Stacked-Die Second Integrated Circuit.”.
The FPGA 102 illustratively includes programmable or configurable logic circuits or “blocks,” shown as CLBs 104, IOBs 106, and programmable interconnects 108, as well as configuration memory 116 for determining the functionality of the FPGA 102. The FPGA 102 may also include an embedded processor block 114, as well as various other dedicated circuitry such as blocks of random access memory (“BRAM 110”), and digital clock management (DCM) blocks 112. Those skilled in the art will appreciate that the FPGA 102 may include other types of logic blocks and circuits in addition to those described herein.
The IOBs 106, the CLBs 104, and the programmable interconnect 108 may be configured to perform a variety of functions. Notably, the CLBs 104 are programmably connectable to each other, and to the IOBs 106, via the programmable interconnect 108. Each CLB slice in turn includes various circuits, such as flip-flops, function generators (e.g., look-up tables (LUTs)), logic gates, and memory. The IOBs 106 are configured to provide input to, and receive output from, the CLBs 104. Configuration information for the CLBs 104, the IOBs 106, and the programmable interconnect 108 is stored in the configuration memory 116. The configuration memory 116 may include static random access memory (SRAM) cells. The IOBs 106 can include transceiver circuitry configured for communication over any of a variety of media, such as wired, wireless, and photonic, whether analog or digital. The DCM blocks 112 provide well-known clock management circuits for managing clock signals within the FPGA 102, such as delay lock loop (DLL) circuits and multiply/divide/de-skew clock circuits. The processor block 114 comprises a microprocessor core, as well as associated control logic.
To enable high data-rate communications, the FPGA can be configured as a multi-port memory controller (MPMC) with built-in arbitration logic as illustrated in FIG. 3. The MPMC may include any number of ports, each of which may be configured to interface with any type of device such as a processor or devices connected to a system bus. The memory controller of FIG. 3 includes general ports 2220 through 222N (collectively referred to as ports 222). The memory controller further includes port arbitration logic 306, data path logic 308, address path logic 310, and control logic 312. Internal data path interfaces of the ports 222 are respectively coupled through a data bus interface 315 to the data path 308 within the MPMC 204. The data path logic 308 includes an interface coupled through a physical (PHY) layer 206 to the memory 208. The address path logic 310 includes an input interface coupled to the address bus 318 and a memory interface coupled through the memory 208 through PHY layer 206. The port arbitration logic 306 includes an interface coupled to the control bus, 319, an interface coupled to the control logic 312, an interface coupled to the data path logic 308, and an interface coupled to the address path logic 310. The control logic 312 includes a memory interface coupled to the memory 208 through a physical (PHY) interface 206.
In operation, the port arbitration logic 306 executes an arbitration algorithm to select one of the ports 222 for access to the memory 208. Notably, a plurality of the ports 222 may provide memory transaction requests to the port arbitration logic 306 simultaneously. The port arbitration logic 306 analyzes all pending transaction requests and provides a request acknowledgment to one of the ports 222 in accordance with the arbitration algorithm. The one of the ports 222 that “wins” then obtains access to the memory 208 and the requested memory transaction is performed. The port arbitration logic 306 provides port select data to each of the address path logic 310 and the data path logic 308. The port select data includes the identity of the selected one of the ports 222. The address path logic 310 receives an address from the selected one of the ports 222 using the port select data. Likewise, the data path logic 308 receives data from the selected one of the ports 222 using the port select data.
After granting a transaction request from one of the ports 222, the port arbitration logic 306 provides a memory transaction request to the control logic 312. The control logic 312 processes the memory transaction request and determines a sequence of sub-transactions required to perform the desired memory transaction. The control logic 312 then drives the data path logic 308, the address path logic 310, and the PHY interface 206 with control signals that execute memory operations on the memory 208. The end result is that the requested memory transaction selected by the arbitration logic 306 is performed.
What is needed is a method for efficiently using the components of an FPGA to form a memory controller in a stacked die arrangement. In particular, a versatile FPGA memory controller is needed that can be easily varied to be used with multiple types of die stacking arrangements.